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Fiberoptic Postamplifier
Main Features
Low-cost IC, available as die or in SOIC16, TSSOP20 and QSOP16 packages. Fabricated in advanced submicron BiCMOS process. Pin-compatible, superior replacement for Signetics NE5224/5. SONET, FDDI, ESCON compatible. Programmable input-signal level detector. Fully differential. Input sensitivity better than 0.8mV at 155Mbps, permitting system sensitivities better than -38dBm (BER 10-9). Fully supports 3.3V and 5V supplies. Differential PECL data and level detect outputs.
MC2045-2
Postamplifier/Quantiser for applications to 200Mbps
General Description
The MC2045-2 is a second-generation, high gain limiting amplifier intended for fiberoptics based communications to 200Mbps. Normally placed following the photodetector and transimpedance or pre-amplifier, the limiting amplifier provides the necessary gain to give ECL compatible logic outputs. The MC2045 also includes a programmable signal-level detector, allowing the user to set thresholds at which the logic outputs are enabled. Though capable of operating over a wide frequency range, the MC2045 has been optimised for 155/200Mbps OC-3/STM-1 and ESCON applications. Note also the MC2044C for applications at 622Mbps and >1Gbps.
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Ordering Information
Part Number MC2045-2S16 MC2045-2T20 MC2045-2Q16 MC2045-2DIEWP MC2045-2WAFER Pin Package SOIC16 TSSOP20 QSOP16 Waffle Pack Expanded whole 8" on a 10" grip ring
V ccA
C azp C azn
V ccE
D in D in
L im itin g Amp.
ECL B u ffe r
D out D out
Jam B u ffe r
Jam
R e fe r e n c e
V set
L evel D e te c t
SD B u ffe r
ST ST
G ndA
Cf
G ndE
MC2045-2 Preliminary Issue C
14 October, 1999
Page 1
Absolute Maximum Ratings
Symbol
PTOT VCC TA TJ TSTG
Parameter
Total power dissipation (TSSOP20) Power supply (VCC-GND) Operating ambient Junction temperature Storage temperature
Rating
TBA 6 -40 to +85 150 -65 to +150
Units
mW V C C C
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reliable operation at these extremes for any length of time is not implied.
Recommended Operating Conditions
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Symbol
VCC TA
Parameter
Power supply (VCC-GND) Operating ambient
Rating
3.0 to 5.5 -40 to +85
Units
V C
DC Electrical Characteristics
Symbol
VIN VOS VN VTH VHYS IINL ICC
Parameter
Input signal voltage Single-ended: (DIN) Differential: Input offset voltage Input RMS noise in 100MHz Input level detect programmability Level detect hysteresis (optical) JAM input current (at 0V) Supply current (no ECL loads)
1
Min
0.8 1.6 2 1.75 -10 -
Typ
2.25 -
Max
400 800 50 85 20 2.75 10 35
Units
mVp-p V V mVp-p dB A mA
AC Electrical Characteristics
Symbol
BW RIN CIN TPWD TR,TF RF TLD
Parameter
Bandwidth: Upper -3dB point Lower -3dB point
Min
1.5 14 0.5
Typ
-
Max
100
Units
KHz MHz k pF ns ns k s
Input resistance Input capacitance Pulse Width Distortion ECL out rise/fall times (20-80% points) Level detect filter resistance Level detect time constant
4.5 1.0 25 1
2 0.3 2.0 41 2.0
1
0.8mV is worst case sensitivity @BER10-9
MC2045-2 Preliminary Issue C
14 October, 1999
Page 2
Pin Descriptions1
Name Function SOIC16 / QSOP16 Pin #
1 2 3
Die Bond #
TSSOP2 0 Pin #
1 2 4
CAZN CAZP GNDA
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DIN DINB VCCA
CF Jam STb
ST
GNDE
DOUTB DOUT VCCE
VSET
NC NC
1
Auto-zero capacitor pin. Connect CAZ between this pin and CAZP. See CAZN Analogue section ground pin. Connect to most negative supply. Must be at the same potential as GNDE. See application diagram. Differential data input. Inverse differential data input Analogue section power pin. Connect to most positive supply. Must be at the same potential as VCCE. See application diagram Level-detect filter capacitor pin. Connect the capacitor between here and VCCA ECL compatible input controlling DOUT output buffers (Pins 12&13). Logical inverse of ST. Normally connected on the PCB to Jam to enable automatic signal-threshold function to operate. Input signal-level status. This ECL2 output is LOW when the input signal is below the threshold set by the user. This is a differential output. Digital section ground pin. Connect to the most negative supply. Must be at the same potential as GNDA. See application diagram Logical inverse of Pin 13. JAM high forces DOUTB high. ECL compatible differential data output. JAM high forces DOUT low. Digital/Output section power pin. Connect to the most positive supply. De-couple using ferrite bead/capacitors. See diagram. Input threshold-level setting circuit. Connect to analogue ground via a resistor. See application diagram Not connected. Compatible with NE5224/5 PCBs. Not connected.
1 2 4
4 5 6
5 6 3
5 6 7
7 8 9
9 11 12
8 11 12
10
13
13
11
14, 15
14, 15
12 13 14
16 17 18, 19
16 17 18, 19
16
20
20
15
3 9, 10
ECL outputs are 100k compatible
Microcosm MC2044C/MC2045-2 Compatibility
The MC2044C and MC2045-2 are pin and functionally compatible, except that the MC2045-2 has reduced bandwidth throughout, to maximise sensitivity at 155/200Mbps. In addition, the MC2044C has CMOS-level outputs on the ST/STb pins, whereas the MC2045-2 has ECL levels.
MC2045-2 Preliminary Issue C
14 October, 1999
Page 3
Signal Path Description Input biasing
The Data Input pins are internally DC biased at approximately 4V, via the Rin resistors. Although the MC2045-2 can be DC coupled, normally it will be AC coupled, using capacitors C1 & C2. Note that Rin and C1,2 form a filter to low frequencies. The capacitors must therefore be large enough to pass the lowest input frequencies (consecutive `1's or `0's) of interest. For example, setting C1,2 to 10nF will give a typical -3dB point of approx. 3.5KHz.
Autozero circuit
The MC2045-2 includes an autozero circuit. In the absence of data, the feedback amplifier and summing circuit cancel the inherent offset voltage of the signal path, keeping the comparator at its toggle point. The time constant of this circuit is set by the combination of RAZ and CAZ, but is not critical. CAZ is normally set to 10nF.
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Power supply decoupling & optimising sensitivity
The MC2045-2 is not expected to require ferrite beads in order to give adequate performance. However, if pin-compatibility with the Microcosm MC2044C is preferred, or optimum MC2045-2 sensitivity required, the VCCA(3) and GNDA(6) pins of the MC2045-2 should each be connected to their respective power rails via a BLM31A601SPT (Murata) ferrite suppressor. See the diagram, below. The lower-cost BLM21A601SPT has not been tested, but would also be expected to work well.
Forward Gain Path block diagram.
Caz 10nF
Optional Surfacemount Ferrite beads
VccE
Raz 10k Raz 10k
VccA
Vcc
C1
Rin 10k
Rin 10k
Din
Comparator
Dout Dout
Din
C2
GndE Gnd
Rset 0-2k typ. G ndA
Gnd
MC2045-2 Preliminary Issue C
14 October, 1999
Page 4
Level detector
The MC2045-2 provides for programmable input-signal level detection, and this may be used to automatically force the data outputs to a known state if the input signal falls below threshold. This is normally used to allow data to propagate only when the signal is above the Bit-Error-Rate (BER) requirement. It therefore also stops the data outputs toggling due to noise when no signal is present. The input data is first amplified, with the level of amplification set by RSET, then rectified and low-pass filtered before being compared with a reference voltage. The low-pass filter is controlled by CF, and 10nF will provide a nominal 1s time constant, thus avoiding false triggering due to noise spikes. The comparator has the equivalent of approx. 2.25dB (typ.) of optical hysteresis, operating either side of the set level. To complete the automatic level detect function, STb should be connected to the JAM input (See level detect diagram, above), thus forcing the data outputs to logical zero when the signal falls below threshold. Note that for compatibility with the NE5224/5, Pin 15 on the SOIC16-packaged MC2045-2 is not connected to the die (`NC'). On the NE5224/5 this pin is VREF, and a R1/R2 voltage divider is used to generate VSET. Microcosm's solution requires only one resistor, whilst remaining compatible with the NE5224/5. Note that RSET must be connected, even if the Level-Detect function is not required.
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Level D etect block diagram .
C1
VccA Cf 10nF
G ndE
D in
R ectifier
D in
C2
Low-pass Filter
2.2k
ST ST
R eference Voltage
Jam
2.2k
Rset 0-2k typ. G ndA
G ndE
Application Note on 3.3V Operation.
When running PECL at 3.3V the output pull-downs need to be lower than 300 when running into a capacitively coupled 50ohm load.
MC2045-2 Preliminary Issue C
14 October, 1999
Page 5
A 50ohm resistor driven by a capacitively coupled 0.8V signal will have +/- 8mA flowing in it. The output of an ECL circuit cannot sink current, the pull-down has to do this. If logic '0' is 1.6volt below VCC, then it is 1.4V above GND, assuming VCC is 3.0V minimum. The pull-down must be less than 175 to still sink the 8mA. Actually, because the emitter of a transistor does not go from low to high resistance suddenly, but inversely with emitter current, so some current must always flow to maintain a low output resistance. This indicates that 150 pulldowns should be used. Now the circuit sees not 50, but a 150 50 = 37.5 ac load, and so you will get a smaller voltage swing than is normal for VCC=5V. If now you operate this circuit at VCC= 5.5V you get an average current in the pull-down. (5.5-1.2)/150 = 28mA. Users should therefore decide in advance whether it is a 3.3V or 5V power supply and set the external pull-downs accordingly.
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Similarly, if the user is able to use higher impedance lines matched to a higher impedance load, then less pull-down current is required, e.g. Rpulldown=220ohms if Zload=75ohms for 3.3V operation. Bare Die
Die layout (not to scale)
VccA G ndA Din Dinb 0.96mm G ndA VccA
M C2045-2 M icrocosm
Cazp 2
Cazn
Vset
VccE VccE Dout Doutb
4
3
1
G ndE G ndE
Cf
Vset2
Jam
STb
ST
1.44mm
I/O Pad openings are 85 square Pad pitch min. 150
VSET and VSET2 are alternative inputs to the same `Vset' function. Connect one or other, not both. The 2 sets of VCCA and GNDA on the left of the die (Die pins 3,7 and 4,8) are to accommodate certain customer applications. Only one pair need be connected, though no harm will result from both pairs being connected. On the TSSOP package pairs of VccE and GNDE connections are brought out, and all should be connected.
MC2045-2 Preliminary Issue C
14 October, 1999
Page 6
Packaged Devices
MC2045-2 Pinouts: drawings not to scale 1 Cazn Cazp
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1 Cazn Vset NC Cazp NC GndA Din Dinb VccA Cf NC NC 10 Microcosm MC2045-2
20 Vset VccE VccE Dout Doutb GndE GndE ST STb Jam 11
16
GndA Din Dinb VccA Cf Jam
Microcosm MC2045-2
VccE Dout Doutb GndE ST STb
9 8 4.3mm x 3.6mm QSOP16 150Mil, Narrow-body SOIC16
6.5x4.4mm TSSOP20 package
MC2045-2 Preliminary Issue C
14 October, 1999
Page 7
World Wide Sales Offices
Headquarters
Newport Beach
Mindspeed Technologies 4000 MacArthur Boulevard, East Tower Newport Beach, CA 92660 Phone: (949) 579-3000
Americas
US Southwest/Pacific Southwest
Newbury Park Phone: (805) 786-2000 Fax: (805) 480-4486
Europe
Europe Central Germany, Switzerland Eastern Europe and Turkey
Phone: (49) 89 829 1320 Fax: (49) 89 834 2734
US Northwest/Pacific Northwest
Santa Clara Phone: (408) 423-4500 Fax: (408) 249-7113
Europe Mediterranean Italy, Spain and Portugal
Phone: (39) 02 9317 9911 Fax: (39) 02 9317 9913
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Phone: (630) 799-9300 Fax: (630) 799-9325
Europe North UK, Ireland and Scandinavia
Phone: 44 (0) 118 920 9500 Fax: 44 (0) 118 920 9595
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Phone: 44 (0) 1925-661968 Fax: 44 (0) 1925-661800
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Phone: (613) 271-2358 Fax: (613) 271-2359
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Phone: +33 (0) 1 56 30 80 40 Fax: +33 (0) 1 56 30 80 20
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Phone: 82-2-565-2880 Fax: 82-2-528-4301
Mindspeed Technologies Japan Company Limited.
Phone: (81-3) 5380 1730 Fax: (81-3) 5371 1501

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